A critical parameter in the design of insulated gate power semiconductor devices such as insulated gate field effect transistors (e.g., MOSFETs) and insulated gate bipolar transistors (IGBTs) is the forward on-state resistance because it determines the maximum current carrying capability of the device. With respect to power MOSFETs, the on-state resistance is the total resistance between the source and drain terminals during forward conduction. This total resistance can be determined by summing the resistance contributions of the MOSFET's source region, channel region, drift region and drain/substrate region. Determination of the total resistance for DMOS-type power MOSFETs is more fully described and illustrated in section 7.4.4 of a textbook by B. J. Baliga entitled Power Semiconductor Devices, PWS Publishing Co. (ISBN 0-534-94098-6) (1995).
However, while it may be advantageous to reduce the resistance of each of these regions to minimize forward on-state resistance, the resistance of the drift region generally cannot be minimized without significantly reducing the breakdown voltage of the device. As shown in FIGS. 1A through 1C, a conventional trench DMOS transistor has a body layer 4 which is formed on a main surface of a semiconductor substrate 1 and doped with a p type impurity, a trench which is formed passing through the body layer 4, a gate oxide layer 2 which is formed on the sidewalls and the bottom of the trench, a gate polysilicon layer 3 which is formed on the gate oxide layer 2 and filled in the trench, and two source contact regions 5 which are formed on both upper sides of the gate polysilicon layer 3 and doped with an n.sup.+ type impurity.
In such a trench DMOS transistor, a drain electrode is connected to the back surface of the semiconductor substrate 1, and a source electrode is commonly connected to the two source contact regions 5 and the body layer 4, and a gate electrode is connected to the gate polysilicon layer 3 which is filled in the trench. The semiconductor substrate 1 consists of an n.sup.+ type drain region 1a doped with a high concentration impurity and an n type drift region 1b doped with a low concentration impurity.
When a voltage signal is applied to said trench DMOS transistor, two channels 6a and 6b are vertically formed along the side surfaces of the gate oxide layer 3, as shown in FIG. 1C, between the source contact regions 5 and the drift region 1b. Because the conventional trench DMOS transistor includes on trench, a current signal flows through only two channels which are formed along both sidewalls of the trench. Moreover, because the area occupied by two channels in the conventional transistor is relatively small as compared to the area occupied by the source contact regions 5 and the body layer 4 under a source electrode, the amount of current flowing through the channels is typically insufficient to provide large current carrying capability. The conventional trench DMOS transistor has another problem in that the gate contact area is typically limited due to the structure of the unit cells which, as illustrated in FIG. 1A, are electrically connected by the gate polysilicon layer 3, and a portion 3a of the gate polysilicon layer surrounded by four cells is not wider in area than the other portion 3b.
Thus, notwithstanding the above described insulated gate semiconductor devices including power MOSFETs and IGBTs, there continues to be a need for devices which have both high current carrying capability and high breakdown voltages.